Test MP+dmb.syw0w4+pos-pospw0-ctrlisbw0w0

AArch64 MP+dmb.syw0w4+pos-pospw0-ctrlisbw0w0
"DMB.SYdWWw0w4 Rfew4P PosRR PosRRPw0 DpCtrlIsbdRw0w0 Frew0w0"
Cycle=PosRR PosRRPw0 DpCtrlIsbdRw0w0 Frew0w0 DMB.SYdWWw0w4 Rfew4P
Relax=PosRR
Safe=[Fre,w0,DMB.SYdWW,w4,Rfe] DpCtrlIsbdR w0
Generator=diy7 (version 7.50+1(dev))
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMB.SYdWWw0w4 Rfew4P PosRR PosRRPw0 DpCtrlIsbdRw0w0 Frew0w0
{
uint64_t y; uint64_t x; uint64_t 1:X4; uint64_t 1:X0;

0:X0=0x1010101; 0:X1=x; 0:X2=0x1010101; 0:X3=y;
1:X1=y; 1:X5=x;
}
 P0             | P1           ;
 STR W0,[X1]    | LDR X0,[X1]  ;
 DMB SY         | LDR X2,[X1]  ;
 STR W2,[X3,#4] | LDR W3,[X1]  ;
                | CBNZ X3,LC00 ;
                | LC00:        ;
                | ISB          ;
                | LDR W4,[X5]  ;
Observed
    y=0x101010100000000; x=0x1010101; 1:X4=0x0; 1:X0=0x101010100000000;