Test SB+posw4w4+posq0w0

AArch64 SB+posw4w4+posq0w0
"PosWRw4w4 Frew4q0 PosWRq0w0 Frew0w4"
Cycle=Frew0w4 PosWRw4w4 Frew4q0 PosWRq0w0
Relax=
Safe=Frew0P Frew4P PosWRw4P PosWRq0P
Prefetch=
Com=Fr Fr
Orig=PosWRw4w4 Frew4q0 PosWRq0w0 Frew0w4
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 0:X3; uint64_t 0:X2;

0:X0=0x1010101; 0:X1=x;
1:X0=0x202020202020202; 1:X1=x;
}
 P0             | P1          ;
 STR W0,[X1,#4] | STR X0,[X1] ;
 LDR W2,[X1,#4] | LDR W2,[X1] ;
 LDR X3,[X1]    | LDR X3,[X1] ;
Observed
    x=0x202020202020202; 1:X3=0x202020202020202; 1:X2=0x2020202; 0:X3=0x101010102020202; 0:X2=0x1010101;