Test S+poq0w4-posw4w0+poq0w4-posw4w4

AArch64 S+poq0w4-posw4w0+poq0w4-posw4w4
"PodWWq0w4 PosWWw4w0 Rfew0q0 PodRWq0w4 PosWWw4w4 Wsew4q0"
Cycle=Rfew0q0 PodRWq0w4 PosWWw4w4 Wsew4q0 PodWWq0w4 PosWWw4w0
Relax=[PodWWq0w4,PosWWw4w0] [PodRWq0w4,PosWWw4w4]
Safe=Rfew0q0 Wsew4q0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=PodWWq0w4 PosWWw4w0 Rfew0q0 PodRWq0w4 PosWWw4w4 Wsew4q0
{
uint64_t y; uint64_t x; uint64_t 1:X5; uint64_t 1:X0;

0:X0=0x303030303030303; 0:X1=x; 0:X2=0x1010101; 0:X3=y; 0:X4=0x2020202;
1:X1=y; 1:X2=0x1010101; 1:X3=x; 1:X4=0x2020202;
}
 P0             | P1             ;
 STR X0,[X1]    | LDR X0,[X1]    ;
 STR W2,[X3,#4] | STR W2,[X3,#4] ;
 STR W4,[X3]    | STR W4,[X3,#4] ;
                | LDR X5,[X3]    ;
Observed
    y=0x101010102020202; x=0x303030303030303; 1:X5=0x202020203030303; 1:X0=0x0;