Test S+poq0w0-posw0w0s002

AArch64 S+poq0w0-posw0w0s002
"PodWRq0w0 PosRWw0w0 Rfew0q0 PodRWq0w0 PosWWw0w0 Wsew0q0"
Cycle=PosWWw0w0 Wsew0q0 PodWRq0w0 PosRWw0w0 Rfew0q0 PodRWq0w0
Relax=[PodWRq0w0,PosRWw0w0] [PodRWq0w0,PosWWw0w0]
Safe=Rfew0q0 Wsew0q0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=PodWRq0w0 PosRWw0w0 Rfew0q0 PodRWq0w0 PosWWw0w0 Wsew0q0
{
uint64_t y; uint64_t x; uint64_t 1:X5; uint64_t 1:X0; uint64_t 0:X2;

0:X0=0x303030303030303; 0:X1=x; 0:X3=y; 0:X4=0x1010101;
1:X1=y; 1:X2=0x1010101; 1:X3=x; 1:X4=0x2020202;
}
 P0          | P1          ;
 STR X0,[X1] | LDR X0,[X1] ;
 LDR W2,[X3] | STR W2,[X3] ;
 STR W4,[X3] | STR W4,[X3] ;
             | LDR X5,[X3] ;
Observed
    y=0x1010101; x=0x303030303030303; 1:X5=0x303030302020202; 1:X0=0x1010101; 0:X2=0x0;
and y=0x1010101; x=0x303030303030303; 1:X5=0x303030302020202; 1:X0=0x0; 0:X2=0x0;