Test R+posw4q0+posw0w0

AArch64 R+posw4q0+posw0w0
"PosWWw4q0 Wseq0w0 PosWRw0w0 Frew0w4"
Cycle=PosWRw0w0 Frew0w4 PosWWw4q0 Wseq0w0
Relax=
Safe=Frew0P PosWRw0P PosWWw4P Wseq0P
Prefetch=
Com=Ws Fr
Orig=PosWWw4q0 Wseq0w0 PosWRw0w0 Frew0w4
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 0:X3;

0:X0=0x1010101; 0:X1=x; 0:X2=0x202020202020202;
1:X0=0x3030303; 1:X1=x;
}
 P0             | P1          ;
 STR W0,[X1,#4] | STR W0,[X1] ;
 STR X2,[X1]    | LDR W2,[X1] ;
 LDR X3,[X1]    | LDR X3,[X1] ;
Observed
    x=0x202020202020202; 1:X3=0x202020203030303; 1:X2=0x3030303; 0:X3=0x202020202020202;