Test R+posq0w0+posw4w4

AArch64 R+posq0w0+posw4w4
"PosWWq0w0 Wsew0w4 PosWRw4w4 Frew4q0"
Cycle=Wsew0w4 PosWRw4w4 Frew4q0 PosWWq0w0
Relax=
Safe=Wsew0P Frew4P PosWRw4P PosWWq0P
Prefetch=
Com=Ws Fr
Orig=PosWWq0w0 Wsew0w4 PosWRw4w4 Frew4q0
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 0:X3;

0:X0=0x101010101010101; 0:X1=x; 0:X2=0x2020202;
1:X0=0x3030303; 1:X1=x;
}
 P0          | P1             ;
 STR X0,[X1] | STR W0,[X1,#4] ;
 STR W2,[X1] | LDR W2,[X1,#4] ;
 LDR X3,[X1] | LDR X3,[X1]    ;
Observed
    x=0x101010102020202; 1:X3=0x303030302020202; 1:X2=0x3030303; 0:X3=0x101010102020202;