Test R+posq0q0+posw0w0

AArch64 R+posq0q0+posw0w0
"PosWWq0q0 Wseq0w0 PosWRw0w0 Frew0q0"
Cycle=PosWRw0w0 Frew0q0 PosWWq0q0 Wseq0w0
Relax=
Safe=Frew0P PosWRw0P Wseq0P PosWWq0P
Prefetch=
Com=Ws Fr
Orig=PosWWq0q0 Wseq0w0 PosWRw0w0 Frew0q0
{
uint64_t x; uint64_t 1:X3; uint64_t 1:X2; uint64_t 0:X3;

0:X0=0x101010101010101; 0:X1=x; 0:X2=0x202020202020202;
1:X0=0x3030303; 1:X1=x;
}
 P0          | P1          ;
 STR X0,[X1] | STR W0,[X1] ;
 STR X2,[X1] | LDR W2,[X1] ;
 LDR X3,[X1] | LDR X3,[X1] ;
Observed
    x=0x202020202020202; 1:X3=0x202020203030303; 1:X2=0x3030303; 0:X3=0x202020202020202;