Test R+poq0w4-posw4w4+poq0w0-posw0w4002

AArch64 R+poq0w4-posw4w4+poq0w0-posw0w4002
"PodWWq0w4 PosWWw4w4 Wsew4q0 PodWRq0w0 PosRRw0w4 Frew4q0"
Cycle=PosRRw0w4 Frew4q0 PodWWq0w4 PosWWw4w4 Wsew4q0 PodWRq0w0
Relax=[PodWRq0w0,PosRRw0w4] [PodWWq0w4,PosWWw4w4]
Safe=Frew4q0 Wsew4q0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=PodWWq0w4 PosWWw4w4 Wsew4q0 PodWRq0w0 PosRRw0w4 Frew4q0
{
uint64_t y; uint64_t x; uint64_t 1:X4; uint64_t 1:X2; uint64_t 0:X5;

0:X0=0x101010101010101; 0:X1=x; 0:X2=0x1010101; 0:X3=y; 0:X4=0x2020202;
1:X0=0x303030303030303; 1:X1=y; 1:X3=x;
}
 P0             | P1             ;
 STR X0,[X1]    | STR X0,[X1]    ;
 STR W2,[X3,#4] | LDR W2,[X3]    ;
 STR W4,[X3,#4] | LDR W4,[X3,#4] ;
 LDR X5,[X3]    |                ;
Observed
    y=0x303030303030303; x=0x101010101010101; 1:X4=0x1010101; 1:X2=0x1010101; 0:X5=0x202020203030303;
and y=0x303030303030303; x=0x101010101010101; 1:X4=0x0; 1:X2=0x0; 0:X5=0x202020203030303;