Test R+poq0w0-posw0w0s001

AArch64 R+poq0w0-posw0w0s001
"PodWWq0w0 PosWWw0w0 Wsew0q0 PodWRq0w0 PosRRw0w0 Frew0q0"
Cycle=PosWWw0w0 Wsew0q0 PodWRq0w0 PosRRw0w0 Frew0q0 PodWWq0w0
Relax=[PodWWq0w0,PosWWw0w0] [PodWRq0w0,PosRRw0w0]
Safe=Frew0q0 Wsew0q0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Ws Fr
Orig=PodWWq0w0 PosWWw0w0 Wsew0q0 PodWRq0w0 PosRRw0w0 Frew0q0
{
uint64_t y; uint64_t x; uint64_t 1:X4; uint64_t 1:X2; uint64_t 0:X5;

0:X0=0x101010101010101; 0:X1=x; 0:X2=0x1010101; 0:X3=y; 0:X4=0x2020202;
1:X0=0x303030303030303; 1:X1=y; 1:X3=x;
}
 P0          | P1          ;
 STR X0,[X1] | STR X0,[X1] ;
 STR W2,[X3] | LDR W2,[X3] ;
 STR W4,[X3] | LDR W4,[X3] ;
 LDR X5,[X3] |             ;
Observed
    y=0x303030303030303; x=0x101010101010101; 1:X4=0x0; 1:X2=0x0; 0:X5=0x303030302020202;