Test 2+2W+posw0w0+posq0w4

AArch64 2+2W+posw0w0+posq0w4
"PosWWw0w0 Wsew0q0 PosWWq0w4 Wsew4w0"
Cycle=PosWWw0w0 Wsew0q0 PosWWq0w4 Wsew4w0
Relax=
Safe=Wsew0P PosWWw0P Wsew4P PosWWq0P
Prefetch=
Com=Ws Ws
Orig=PosWWw0w0 Wsew0q0 PosWWq0w4 Wsew4w0
{
uint64_t x; uint64_t 1:X3; uint64_t 0:X3;

0:X0=0x1010101; 0:X1=x; 0:X2=0x2020202;
1:X0=0x303030303030303; 1:X1=x; 1:X2=0x4040404;
}
 P0          | P1             ;
 STR W0,[X1] | STR X0,[X1]    ;
 STR W2,[X1] | STR W2,[X1,#4] ;
 LDR X3,[X1] | LDR X3,[X1]    ;
Observed
    x=0x404040403030303; 1:X3=0x404040403030303; 0:X3=0x404040402020202;