Test SB+posw0q0-poq0q0-posq0w0s007

Executions for behaviour: "0:X2=0x2020202 ; 0:X5=0x1010101 ; 0:X6=0x101010101010101 ; 1:X2=0x101010102020202 ; 1:X5=0x1010101 ; 1:X6=0x101010101010101 ; x=0x101010101010101 ; y=0x101010101010101"

AArch64 SB+posw0q0-poq0q0-posq0w0s007
"PosWRw0q0 PodRWq0q0 PosWRq0w0 Frew0w0 PosWRw0q0 PodRWq0q0 PosWRq0w0 Frew0w0"
Cycle=Frew0w0 PosWRw0q0 PodRWq0q0 PosWRq0w0 Frew0w0 PosWRw0q0 PodRWq0q0 PosWRq0w0
Relax=[PosWRw0q0,PodRWq0q0,PosWRq0w0]
Safe=Frew0w0
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=PosWRw0q0 PodRWq0q0 PosWRq0w0 Frew0w0 PosWRw0q0 PodRWq0q0 PosWRq0w0 Frew0w0
{
uint64_t y; uint64_t x; uint64_t 1:X6; uint64_t 1:X5; uint64_t 1:X2; uint64_t 0:X6; uint64_t 0:X5; uint64_t 0:X2;

0:X0=0x2020202; 0:X1=x; 0:X3=0x101010101010101; 0:X4=y;
1:X0=0x2020202; 1:X1=y; 1:X3=0x101010101010101; 1:X4=x;
}
 P0          | P1          ;
 STR W0,[X1] | STR W0,[X1] ;
 LDR X2,[X1] | LDR X2,[X1] ;
 STR X3,[X4] | STR X3,[X4] ;
 LDR W5,[X4] | LDR W5,[X4] ;
 LDR X6,[X4] | LDR X6,[X4] ;
Observed
    y=0x101010101010101; x=0x101010101010101; 1:X6=0x101010101010101; 1:X5=0x1010101; 1:X2=0x101010102020202; 0:X6=0x101010101010101; 0:X5=0x1010101; 0:X2=0x2020202;