Test SB+poq0w0-posw0w0+poq0w4-posw4w0

Executions for behaviour: "0:X4=0x1010101 ; 0:X5=0x202020201010101 ; 1:X4=0x0 ; x=0x101010102020202 ; y=0x202020202020202"

Executions for behaviour: "0:X4=0x1010101 ; 0:X5=0x202020201010101 ; 1:X4=0x0 ; x=0x202020202020202 ; y=0x202020202020202"

Executions for behaviour: "0:X4=0x1010101 ; 0:X5=0x202020201010101 ; 1:X4=0x2020202 ; x=0x101010102020202 ; y=0x202020202020202"

AArch64 SB+poq0w0-posw0w0+poq0w4-posw4w0
"PodWWq0w0 PosWRw0w0 Frew0q0 PodWWq0w4 PosWRw4w0 Frew0q0"
Cycle=PosWRw0w0 Frew0q0 PodWWq0w4 PosWRw4w0 Frew0q0 PodWWq0w0
Relax=[PodWWq0w0,PosWRw0w0] [PodWWq0w4,PosWRw4w0]
Safe=Frew0q0
Prefetch=0:x=F,0:y=T,1:y=F,1:x=T
Com=Fr Fr
Orig=PodWWq0w0 PosWRw0w0 Frew0q0 PodWWq0w4 PosWRw4w0 Frew0q0
{
uint64_t y; uint64_t x; uint64_t 1:X4; uint64_t 0:X5; uint64_t 0:X4;

0:X0=0x202020202020202; 0:X1=x; 0:X2=0x1010101; 0:X3=y;
1:X0=0x202020202020202; 1:X1=y; 1:X2=0x1010101; 1:X3=x;
}
 P0          | P1             ;
 STR X0,[X1] | STR X0,[X1]    ;
 STR W2,[X3] | STR W2,[X3,#4] ;
 LDR W4,[X3] | LDR W4,[X3]    ;
 LDR X5,[X3] |                ;
Observed
    y=0x202020202020202; x=0x101010102020202; 1:X4=0x2020202; 0:X5=0x202020201010101; 0:X4=0x1010101;
and y=0x202020202020202; x=0x202020202020202; 1:X4=0x0; 0:X5=0x202020201010101; 0:X4=0x1010101;
and y=0x202020202020202; x=0x101010102020202; 1:X4=0x0; 0:X5=0x202020201010101; 0:X4=0x1010101;