Test S+poq0w4-posw4w4s002

Executions for behaviour: "0:X2=0x0 ; 1:X0=0x0 ; 1:X5=0x202020203030303 ; x=0x303030303030303 ; y=0x101010100000000"

Executions for behaviour: "0:X2=0x0 ; 1:X0=0x101010100000000 ; 1:X5=0x202020203030303 ; x=0x303030303030303 ; y=0x101010100000000"

AArch64 S+poq0w4-posw4w4s002
"PodWRq0w4 PosRWw4w4 Rfew4q0 PodRWq0w4 PosWWw4w4 Wsew4q0"
Cycle=PosWWw4w4 Wsew4q0 PodWRq0w4 PosRWw4w4 Rfew4q0 PodRWq0w4
Relax=[PodWRq0w4,PosRWw4w4] [PodRWq0w4,PosWWw4w4]
Safe=Rfew4q0 Wsew4q0
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Rf Ws
Orig=PodWRq0w4 PosRWw4w4 Rfew4q0 PodRWq0w4 PosWWw4w4 Wsew4q0
{
uint64_t y; uint64_t x; uint64_t 1:X5; uint64_t 1:X0; uint64_t 0:X2;

0:X0=0x303030303030303; 0:X1=x; 0:X3=y; 0:X4=0x1010101;
1:X1=y; 1:X2=0x1010101; 1:X3=x; 1:X4=0x2020202;
}
 P0             | P1             ;
 STR X0,[X1]    | LDR X0,[X1]    ;
 LDR W2,[X3,#4] | STR W2,[X3,#4] ;
 STR W4,[X3,#4] | STR W4,[X3,#4] ;
                | LDR X5,[X3]    ;
Observed
    y=0x101010100000000; x=0x303030303030303; 1:X5=0x202020203030303; 1:X0=0x101010100000000; 0:X2=0x0;
and y=0x101010100000000; x=0x303030303030303; 1:X5=0x202020203030303; 1:X0=0x0; 0:X2=0x0;