Test 2+2W+posw4q0-poq0q0-posq0w4+posw0q0-poq0q0-posq0w4002

Executions for behaviour: "y=0x202020201010101 ; x=0x101010103030303 ; 1:X6=0x101010103030303 ; 1:X3=0x303030303030303 ; 1:X2=0x202020203030303 ; 0:X6=0x202020201010101"

Executions for behaviour: "y=0x202020201010101 ; x=0x101010103030303 ; 1:X6=0x101010103030303 ; 1:X3=0x0 ; 1:X2=0x202020203030303 ; 0:X6=0x202020201010101"

AArch64 2+2W+posw4q0-poq0q0-posq0w4+posw0q0-poq0q0-posq0w4002
"PosWWw4q0 PodWWq0q0 PosWWq0w4 Wsew4w0 PosWRw0q0 PodRRq0q0 PosRWq0w4 Wsew4w4"
Cycle=PosWRw0q0 PodRRq0q0 PosRWq0w4 Wsew4w4 PosWWw4q0 PodWWq0q0 PosWWq0w4 Wsew4w0
Relax=[PosWRw0q0,PodRRq0q0,PosRWq0w4] [PosWWw4q0,PodWWq0q0,PosWWq0w4]
Safe=Wsew4w0 Wsew4w4
Prefetch=0:x=F,0:y=W,1:y=F,1:x=W
Com=Ws Ws
Orig=PosWWw4q0 PodWWq0q0 PosWWq0w4 Wsew4w0 PosWRw0q0 PodRRq0q0 PosRWq0w4 Wsew4w4
{
uint64_t y; uint64_t x; uint64_t 1:X6; uint64_t 1:X3; uint64_t 1:X2; uint64_t 0:X6;

0:X0=0x2020202; 0:X1=x; 0:X2=0x303030303030303; 0:X3=0x101010101010101; 0:X4=y; 0:X5=0x2020202;
1:X0=0x3030303; 1:X1=y; 1:X4=x; 1:X5=0x1010101;
}
 P0             | P1             ;
 STR W0,[X1,#4] | STR W0,[X1]    ;
 STR X2,[X1]    | LDR X2,[X1]    ;
 STR X3,[X4]    | LDR X3,[X4]    ;
 STR W5,[X4,#4] | STR W5,[X4,#4] ;
 LDR X6,[X4]    | LDR X6,[X4]    ;
Observed
    0:X6=0x202020201010101; 1:X2=0x202020203030303; 1:X3=0x0; 1:X6=0x101010103030303; x=0x101010103030303; y=0x202020201010101;
and 0:X6=0x202020201010101; 1:X2=0x202020203030303; 1:X3=0x303030303030303; 1:X6=0x101010103030303; x=0x101010103030303; y=0x202020201010101;