Test auto/WW-G+WW-G+WW-R+WW-R+WW-R

LISA auto/WW-G+WW-G+WW-R+WW-R+WW-R
(*
 * Result: Sometimes
 * 
 * Process 0 starts (t=196996).
 * 
 * P0 advances one grace period (t=296996).
 * 
 * P1 advances one grace period (t=396997).
 * 
 * P2 goes back a bit less than one grace period (t=297998).
 * 
 * P3 goes back a bit less than one grace period (t=198999).
 * 
 * P4 goes back a bit less than one grace period (t=100000).
 * 
 * Process 0 start at t=196996, process 5 end at t=100000: Cycle allowed.
 *)
{
}
 P0           | P1           | P2                 | P3                 | P4                 ;
 w[once] x0 2 | w[once] x1 2 | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   ;
 f[sync]      | f[sync]      | w[once] x2 2       | w[once] x3 2       | w[once] x4 2       ;
 w[once] x1 1 | w[once] x2 1 | w[once] x3 1       | w[once] x4 1       | w[once] x0 1       ;
              |              | f[rcu_read_unlock] | f[rcu_read_unlock] | f[rcu_read_unlock] ;
Observed
    x4=2; x3=2; x2=2; x1=2; x0=2;
and x4=1; x3=2; x2=2; x1=2; x0=2;
and x4=2; x3=1; x2=2; x1=2; x0=2;
and x4=1; x3=1; x2=2; x1=2; x0=2;
and x4=2; x3=2; x2=2; x1=1; x0=2;
and x4=1; x3=2; x2=2; x1=1; x0=2;
and x4=2; x3=1; x2=2; x1=1; x0=2;
and x4=1; x3=1; x2=2; x1=1; x0=2;
and x4=2; x3=2; x2=2; x1=2; x0=1;
and x4=1; x3=2; x2=2; x1=2; x0=1;
and x4=2; x3=1; x2=2; x1=2; x0=1;
and x4=1; x3=1; x2=2; x1=2; x0=1;
and x4=1; x3=1; x2=1; x1=2; x0=1;
and x4=2; x3=2; x2=2; x1=1; x0=1;
and x4=1; x3=2; x2=2; x1=1; x0=1;
and x4=2; x3=1; x2=2; x1=1; x0=1;
and x4=1; x3=1; x2=2; x1=1; x0=1;