Test auto/WW-G+WW-B+WW-G+WW-G+WW-R

LISA auto/WW-G+WW-B+WW-G+WW-G+WW-R
(*
 * Result: Never
 * 
 * Process 0 starts (t=100000).
 * 
 * P0 advances one grace period (t=200000).
 * 
 * P1 advances slightly (t=200002).
 * 
 * P2 advances one grace period (t=300003).
 * 
 * P3 advances one grace period (t=400004).
 * 
 * P4 goes back a bit less than one grace period (t=301005).
 * 
 * Process 0 start at t=100000, process 5 end at t=301005: Cycle forbidden.
 *)
{
}
 P0           | P1           | P2           | P3           | P4                 ;
 w[once] x0 2 | w[once] x1 2 | w[once] x2 2 | w[once] x3 2 | f[rcu_read_lock]   ;
 f[sync]      | f[mb]        | f[sync]      | f[sync]      | w[once] x4 2       ;
 w[once] x1 1 | w[once] x2 1 | w[once] x3 1 | w[once] x4 1 | w[once] x0 1       ;
              |              |              |              | f[rcu_read_unlock] ;
Observed
    x4=1; x3=2; x2=2; x1=2; x0=2;
and x4=2; x3=1; x2=2; x1=2; x0=2;
and x4=1; x3=1; x2=2; x1=2; x0=2;
and x4=2; x3=2; x2=1; x1=2; x0=2;
and x4=1; x3=2; x2=1; x1=2; x0=2;
and x4=2; x3=1; x2=1; x1=2; x0=2;
and x4=1; x3=1; x2=1; x1=2; x0=2;
and x4=2; x3=2; x2=1; x1=1; x0=2;
and x4=2; x3=1; x2=1; x1=1; x0=2;
and x4=2; x3=2; x2=2; x1=2; x0=1;
and x4=1; x3=2; x2=2; x1=2; x0=1;
and x4=2; x3=1; x2=2; x1=2; x0=1;
and x4=1; x3=1; x2=2; x1=2; x0=1;
and x4=2; x3=2; x2=1; x1=2; x0=1;
and x4=1; x3=2; x2=1; x1=2; x0=1;
and x4=2; x3=1; x2=1; x1=2; x0=1;