Test auto/WR-H+WR-R+WR-R+WR-G+WR-R

LISA auto/WR-H+WR-R+WR-R+WR-G+WR-R
(*
 * Result: Never
 * 
 * Process 0 starts (t=100000).
 * 
 * P0 advances two grace periods (t=300000).
 * 
 * P1 goes back a bit less than one grace period (t=201001).
 * 
 * P2 goes back a bit less than one grace period (t=102002).
 * 
 * P3 advances one grace period (t=202003).
 * 
 * P4 goes back a bit less than one grace period (t=103004).
 * 
 * Process 0 start at t=100000, process 5 end at t=103004: Cycle forbidden.
 *)
{
}
 P0            | P1                 | P2                 | P3            | P4                 ;
 w[once] x0 2  | f[rcu_read_lock]   | f[rcu_read_lock]   | w[once] x3 2  | f[rcu_read_lock]   ;
 f[sync]       | w[once] x1 2       | w[once] x2 2       | f[sync]       | w[once] x4 2       ;
 f[sync]       | r[once] r2 x2      | r[once] r2 x3      | r[once] r2 x4 | r[once] r2 x0      ;
 r[once] r2 x1 | f[rcu_read_unlock] | f[rcu_read_unlock] |               | f[rcu_read_unlock] ;
Observed
    4:r2=0; 3:r2=0; 2:r2=2; 1:r2=2; 0:r2=2;
and 4:r2=2; 3:r2=2; 2:r2=2; 1:r2=2; 0:r2=0;
and 4:r2=0; 3:r2=2; 2:r2=2; 1:r2=2; 0:r2=0;
and 4:r2=0; 3:r2=0; 2:r2=2; 1:r2=2; 0:r2=0;
and 4:r2=2; 3:r2=2; 2:r2=0; 1:r2=2; 0:r2=0;
and 4:r2=0; 3:r2=2; 2:r2=0; 1:r2=2; 0:r2=0;
and 4:r2=0; 3:r2=0; 2:r2=0; 1:r2=2; 0:r2=0;
and 4:r2=2; 3:r2=2; 2:r2=2; 1:r2=0; 0:r2=0;
and 4:r2=0; 3:r2=2; 2:r2=2; 1:r2=0; 0:r2=0;
and 4:r2=2; 3:r2=0; 2:r2=2; 1:r2=0; 0:r2=0;
and 4:r2=0; 3:r2=0; 2:r2=2; 1:r2=0; 0:r2=0;
and 4:r2=2; 3:r2=2; 2:r2=0; 1:r2=0; 0:r2=0;
and 4:r2=0; 3:r2=2; 2:r2=0; 1:r2=0; 0:r2=0;
and 4:r2=2; 3:r2=0; 2:r2=0; 1:r2=0; 0:r2=0;