Test auto/WR-G+WR-R+WR-R+WR-R

LISA auto/WR-G+WR-R+WR-R+WR-R
(*
 * Result: Sometimes
 * 
 * Process 0 starts (t=296997).
 * 
 * P0 advances one grace period (t=396997).
 * 
 * P1 goes back a bit less than one grace period (t=297998).
 * 
 * P2 goes back a bit less than one grace period (t=198999).
 * 
 * P3 goes back a bit less than one grace period (t=100000).
 * 
 * Process 0 start at t=296997, process 4 end at t=100000: Cycle allowed.
 *)
{
}
 P0            | P1                 | P2                 | P3                 ;
 w[once] x0 2  | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   ;
 f[sync]       | w[once] x1 2       | w[once] x2 2       | w[once] x3 2       ;
 r[once] r2 x1 | r[once] r2 x2      | r[once] r2 x3      | r[once] r2 x0      ;
               | f[rcu_read_unlock] | f[rcu_read_unlock] | f[rcu_read_unlock] ;
Observed
    3:r2=0; 2:r2=0; 1:r2=0; 0:r2=0;