Test auto/WR-G+WR-G+WR-G+WR-R+WR-R+WR-R

LISA auto/WR-G+WR-G+WR-G+WR-R+WR-R+WR-R
(*
 * Result: Never
 * 
 * Process 0 starts (t=100000).
 * 
 * P0 advances one grace period (t=200000).
 * 
 * P1 advances one grace period (t=300001).
 * 
 * P2 advances one grace period (t=400002).
 * 
 * P3 goes back a bit less than one grace period (t=301003).
 * 
 * P4 goes back a bit less than one grace period (t=202004).
 * 
 * P5 goes back a bit less than one grace period (t=103005).
 * 
 * Process 0 start at t=100000, process 6 end at t=103005: Cycle forbidden.
 *)
{
}
 P0            | P1            | P2            | P3                 | P4                 | P5                 ;
 w[once] x0 2  | w[once] x1 2  | w[once] x2 2  | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   ;
 f[sync]       | f[sync]       | f[sync]       | w[once] x3 2       | w[once] x4 2       | w[once] x5 2       ;
 r[once] r2 x1 | r[once] r2 x2 | r[once] r2 x3 | r[once] r2 x4      | r[once] r2 x5      | r[once] r2 x0      ;
               |               |               | f[rcu_read_unlock] | f[rcu_read_unlock] | f[rcu_read_unlock] ;
Observed
    5:r2=2; 4:r2=2; 3:r2=2; 2:r2=0; 1:r2=2; 0:r2=2;
and 5:r2=0; 4:r2=2; 3:r2=2; 2:r2=0; 1:r2=2; 0:r2=2;
and 5:r2=2; 4:r2=0; 3:r2=2; 2:r2=0; 1:r2=2; 0:r2=2;
and 5:r2=0; 4:r2=0; 3:r2=2; 2:r2=0; 1:r2=2; 0:r2=2;
and 5:r2=2; 4:r2=2; 3:r2=0; 2:r2=0; 1:r2=2; 0:r2=2;
and 5:r2=0; 4:r2=2; 3:r2=0; 2:r2=0; 1:r2=2; 0:r2=2;
and 5:r2=2; 4:r2=0; 3:r2=0; 2:r2=0; 1:r2=2; 0:r2=2;
and 5:r2=0; 4:r2=0; 3:r2=0; 2:r2=0; 1:r2=2; 0:r2=2;
and 5:r2=2; 4:r2=2; 3:r2=2; 2:r2=2; 1:r2=0; 0:r2=2;
and 5:r2=2; 4:r2=2; 3:r2=0; 2:r2=2; 1:r2=0; 0:r2=2;
and 5:r2=2; 4:r2=2; 3:r2=2; 2:r2=0; 1:r2=0; 0:r2=2;
and 5:r2=0; 4:r2=2; 3:r2=2; 2:r2=0; 1:r2=0; 0:r2=2;
and 5:r2=2; 4:r2=0; 3:r2=2; 2:r2=0; 1:r2=0; 0:r2=2;
and 5:r2=0; 4:r2=0; 3:r2=2; 2:r2=0; 1:r2=0; 0:r2=2;
and 5:r2=2; 4:r2=2; 3:r2=0; 2:r2=0; 1:r2=0; 0:r2=2;
and 5:r2=0; 4:r2=2; 3:r2=0; 2:r2=0; 1:r2=0; 0:r2=2;
and 5:r2=2; 4:r2=0; 3:r2=0; 2:r2=0; 1:r2=0; 0:r2=2;
and 5:r2=0; 4:r2=0; 3:r2=0; 2:r2=0; 1:r2=0; 0:r2=2;
and 5:r2=2; 4:r2=2; 3:r2=2; 2:r2=2; 1:r2=2; 0:r2=0;
and 5:r2=2; 4:r2=2; 3:r2=0; 2:r2=2; 1:r2=2; 0:r2=0;
and 5:r2=2; 4:r2=2; 3:r2=2; 2:r2=0; 1:r2=2; 0:r2=0;
and 5:r2=0; 4:r2=2; 3:r2=2; 2:r2=0; 1:r2=2; 0:r2=0;
and 5:r2=2; 4:r2=0; 3:r2=2; 2:r2=0; 1:r2=2; 0:r2=0;
and 5:r2=0; 4:r2=0; 3:r2=2; 2:r2=0; 1:r2=2; 0:r2=0;
and 5:r2=2; 4:r2=2; 3:r2=0; 2:r2=0; 1:r2=2; 0:r2=0;
and 5:r2=0; 4:r2=2; 3:r2=0; 2:r2=0; 1:r2=2; 0:r2=0;
and 5:r2=2; 4:r2=0; 3:r2=0; 2:r2=0; 1:r2=2; 0:r2=0;
and 5:r2=0; 4:r2=0; 3:r2=0; 2:r2=0; 1:r2=2; 0:r2=0;
and 5:r2=2; 4:r2=2; 3:r2=2; 2:r2=2; 1:r2=0; 0:r2=0;
and 5:r2=2; 4:r2=2; 3:r2=0; 2:r2=2; 1:r2=0; 0:r2=0;
and 5:r2=2; 4:r2=0; 3:r2=0; 2:r2=2; 1:r2=0; 0:r2=0;
and 5:r2=2; 4:r2=2; 3:r2=2; 2:r2=0; 1:r2=0; 0:r2=0;
and 5:r2=0; 4:r2=2; 3:r2=2; 2:r2=0; 1:r2=0; 0:r2=0;
and 5:r2=2; 4:r2=0; 3:r2=2; 2:r2=0; 1:r2=0; 0:r2=0;
and 5:r2=0; 4:r2=0; 3:r2=2; 2:r2=0; 1:r2=0; 0:r2=0;
and 5:r2=2; 4:r2=2; 3:r2=0; 2:r2=0; 1:r2=0; 0:r2=0;
and 5:r2=0; 4:r2=2; 3:r2=0; 2:r2=0; 1:r2=0; 0:r2=0;
and 5:r2=2; 4:r2=0; 3:r2=0; 2:r2=0; 1:r2=0; 0:r2=0;