Test auto/RW-Rs+RW-RD+RW-R+RW-R+RW-R

LISA auto/RW-Rs+RW-RD+RW-R+RW-R+RW-R
(*
 * Result: Sometimes
 * 
 * Process 0 starts (t=396994).
 * 
 * P0 advances slightly (t=396995).
 * 
 * P1 advances slightly (t=396997).
 * 
 * P2 goes back a bit less than one grace period (t=297998).
 * 
 * P3 goes back a bit less than one grace period (t=198999).
 * 
 * P4 goes back a bit less than one grace period (t=100000).
 * 
 * Process 0 start at t=396994, process 5 end at t=100000: Cycle allowed.
 *)
{
 0:r3=x2; x1=y2; 1:r4=y2;
}
 P0                 | P1                 | P2                 | P3                 | P4                 ;
 f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   ;
 r[once] r1 x0      | r[deref] r1 x1     | r[once] r1 x2      | r[once] r1 x3      | r[once] r1 x4      ;
 w[assign] x1 r3    | w[once] r1 1       | w[once] x3 1       | w[once] x4 1       | w[once] x0 1       ;
 f[rcu_read_unlock] | f[rcu_read_unlock] | f[rcu_read_unlock] | f[rcu_read_unlock] | f[rcu_read_unlock] ;
Observed
    4:r1=1; 3:r1=1; 2:r1=1; 1:r1=x2; 0:r1=1;