LISA auto/RW-Rr+RW-RC+RW-R
(*
* Result: Sometimes
*
* Process 0 starts (t=198996).
*
* P0 advances slightly (t=198997).
*
* P1 advances slightly (t=198999).
*
* P2 goes back a bit less than one grace period (t=100000).
*
* Process 0 start at t=198996, process 3 end at t=100000: Cycle allowed.
*)
{
}
P0 | P1 | P2 ;
f[rcu_read_lock] | f[rcu_read_lock] | f[rcu_read_lock] ;
r[once] r1 x0 | r[once] r1 x1 | r[once] r1 x2 ;
w[release] x1 1 | mov r4 (eq r1 r4) | w[once] x0 1 ;
f[rcu_read_unlock] | b[] r4 CTRL1 | f[rcu_read_unlock] ;
| w[once] x2 1 | ;
| CTRL1: | ;
| f[rcu_read_unlock] | ;
Observed
2:r1=1; 1:r1=1; 0:r1=1;