Test auto/RW-Rr+RW-RC+RW-R+RW-R

LISA auto/RW-Rr+RW-RC+RW-R+RW-R
(*
 * Result: Sometimes
 * 
 * Process 0 starts (t=297995).
 * 
 * P0 advances slightly (t=297996).
 * 
 * P1 advances slightly (t=297998).
 * 
 * P2 goes back a bit less than one grace period (t=198999).
 * 
 * P3 goes back a bit less than one grace period (t=100000).
 * 
 * Process 0 start at t=297995, process 4 end at t=100000: Cycle allowed.
 *)
{
}
 P0                 | P1                 | P2                 | P3                 ;
 f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   ;
 r[once] r1 x0      | r[once] r1 x1      | r[once] r1 x2      | r[once] r1 x3      ;
 w[release] x1 1    | mov r4 (eq r1 r4)  | w[once] x3 1       | w[once] x0 1       ;
 f[rcu_read_unlock] | b[] r4 CTRL1       | f[rcu_read_unlock] | f[rcu_read_unlock] ;
                    | w[once] x2 1       |                    |                    ;
                    | CTRL1:             |                    |                    ;
                    | f[rcu_read_unlock] |                    |                    ;
Observed
    3:r1=1; 2:r1=1; 1:r1=1; 0:r1=1;