Test auto/RW-G+RW-Rs+RW-RCD+RW-G+RW-G+RW-R

LISA auto/RW-G+RW-Rs+RW-RCD+RW-G+RW-G+RW-R
(*
 * Result: Never
 * 
 * Process 0 starts (t=100000).
 * 
 * P0 advances one grace period (t=200000).
 * 
 * P1 advances slightly (t=200002).
 * 
 * P2 advances slightly (t=200004).
 * 
 * P3 advances one grace period (t=300005).
 * 
 * P4 advances one grace period (t=400006).
 * 
 * P5 goes back a bit less than one grace period (t=301007).
 * 
 * Process 0 start at t=100000, process 6 end at t=301007: Cycle forbidden.
 *)
{
 1:r3=x3; x2=y3; 2:r4=y3;
}
 P0            | P1                 | P2                 | P3            | P4            | P5                 ;
 r[once] r1 x0 | f[rcu_read_lock]   | f[rcu_read_lock]   | r[once] r1 x3 | r[once] r1 x4 | f[rcu_read_lock]   ;
 f[sync]       | r[once] r1 x1      | r[deref] r1 x2     | f[sync]       | f[sync]       | r[once] r1 x5      ;
 w[once] x1 1  | w[assign] x2 r3    | mov r4 (eq r1 r4)  | w[once] x4 1  | w[once] x5 1  | w[once] x0 1       ;
               | f[rcu_read_unlock] | b[] r4 CTRL2       |               |               | f[rcu_read_unlock] ;
               |                    | w[once] r1 1       |               |               |                    ;
               |                    | CTRL2:             |               |               |                    ;
               |                    | f[rcu_read_unlock] |               |               |                    ;
Observed
    5:r1=1; 4:r1=1; 3:r1=0; 2:r1=y3; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=y3; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=x3; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=1; 2:r1=x3; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=0; 3:r1=1; 2:r1=x3; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=x3; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=x3; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=x3; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=0; 3:r1=0; 2:r1=x3; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=1; 2:r1=x3; 1:r1=0; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=x3; 1:r1=0; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=x3; 1:r1=0; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=x3; 1:r1=0; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=y3; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=y3; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=y3; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=1; 2:r1=x3; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=x3; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=0; 3:r1=1; 2:r1=x3; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=0; 3:r1=1; 2:r1=x3; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=x3; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=x3; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=x3; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=0; 3:r1=0; 2:r1=x3; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=x3; 1:r1=0; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=x3; 1:r1=0; 0:r1=0;