Test auto/RW-G+RW-Rr+RW-Ra+RW-G+RW-R

LISA auto/RW-G+RW-Rr+RW-Ra+RW-G+RW-R
(*
 * Result: Never
 * 
 * Process 0 starts (t=100000).
 * 
 * P0 advances one grace period (t=200000).
 * 
 * P1 advances slightly (t=200002).
 * 
 * P2 advances slightly (t=200004).
 * 
 * P3 advances one grace period (t=300005).
 * 
 * P4 goes back a bit less than one grace period (t=201006).
 * 
 * Process 0 start at t=100000, process 5 end at t=201006: Cycle forbidden.
 *)
{
}
 P0            | P1                 | P2                 | P3            | P4                 ;
 r[once] r1 x0 | f[rcu_read_lock]   | f[rcu_read_lock]   | r[once] r1 x3 | f[rcu_read_lock]   ;
 f[sync]       | r[once] r1 x1      | r[acquire] r1 x2   | f[sync]       | r[once] r1 x4      ;
 w[once] x1 1  | w[release] x2 1    | w[once] x3 1       | w[once] x4 1  | w[once] x0 1       ;
               | f[rcu_read_unlock] | f[rcu_read_unlock] |               | f[rcu_read_unlock] ;
Observed
    4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=1;
and 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=1;
and 4:r1=0; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=1;
and 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=1;
and 4:r1=0; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=1;
and 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=1;
and 4:r1=0; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=1;
and 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=0; 0:r1=1;
and 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=0; 0:r1=1;
and 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=0;
and 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=0;
and 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=0;