Test auto/RW-G+RW-Rr+RW-RC+RW-R+RW-R+RW-R

LISA auto/RW-G+RW-Rr+RW-RC+RW-R+RW-R+RW-R
(*
 * Result: Sometimes
 * 
 * Process 0 starts (t=296993).
 * 
 * P0 advances one grace period (t=396993).
 * 
 * P1 advances slightly (t=396995).
 * 
 * P2 advances slightly (t=396997).
 * 
 * P3 goes back a bit less than one grace period (t=297998).
 * 
 * P4 goes back a bit less than one grace period (t=198999).
 * 
 * P5 goes back a bit less than one grace period (t=100000).
 * 
 * Process 0 start at t=296993, process 6 end at t=100000: Cycle allowed.
 *)
{
}
 P0            | P1                 | P2                 | P3                 | P4                 | P5                 ;
 r[once] r1 x0 | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   ;
 f[sync]       | r[once] r1 x1      | r[once] r1 x2      | r[once] r1 x3      | r[once] r1 x4      | r[once] r1 x5      ;
 w[once] x1 1  | w[release] x2 1    | mov r4 (eq r1 r4)  | w[once] x4 1       | w[once] x5 1       | w[once] x0 1       ;
               | f[rcu_read_unlock] | b[] r4 CTRL2       | f[rcu_read_unlock] | f[rcu_read_unlock] | f[rcu_read_unlock] ;
               |                    | w[once] x3 1       |                    |                    |                    ;
               |                    | CTRL2:             |                    |                    |                    ;
               |                    | f[rcu_read_unlock] |                    |                    |                    ;
Observed
    5:r1=1; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=0; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=0; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=0; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=0;