Test auto/RW-G+RW-G+RW-G+RW-r+RW-C

LISA auto/RW-G+RW-G+RW-G+RW-r+RW-C
(*
 * Result: Never
 * 
 * Process 0 starts (t=100000).
 * 
 * P0 advances one grace period (t=200000).
 * 
 * P1 advances one grace period (t=300001).
 * 
 * P2 advances one grace period (t=400002).
 * 
 * P3 advances slightly (t=400004).
 * 
 * P4 advances slightly (t=400006).
 * 
 * Process 0 start at t=100000, process 5 end at t=400006: Cycle forbidden.
 *)
{
}
 P0            | P1            | P2            | P3              | P4                ;
 r[once] r1 x0 | r[once] r1 x1 | r[once] r1 x2 | r[once] r1 x3   | r[once] r1 x4     ;
 f[sync]       | f[sync]       | f[sync]       | w[release] x4 1 | mov r4 (eq r1 r4) ;
 w[once] x1 1  | w[once] x2 1  | w[once] x3 1  |                 | b[] r4 CTRL4      ;
               |               |               |                 | w[once] x0 1      ;
               |               |               |                 | CTRL4:            ;
Observed
    4:r1=1; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=1;
and 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=1;
and 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=1;
and 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=0;
and 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=0;
and 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=0;
and 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=0;