Test auto/RW-G+RW-G+RW-G+RW-Rs+RW-RD

LISA auto/RW-G+RW-G+RW-G+RW-Rs+RW-RD
(*
 * Result: Never
 * 
 * Process 0 starts (t=100000).
 * 
 * P0 advances one grace period (t=200000).
 * 
 * P1 advances one grace period (t=300001).
 * 
 * P2 advances one grace period (t=400002).
 * 
 * P3 advances slightly (t=400004).
 * 
 * P4 advances slightly (t=400006).
 * 
 * Process 0 start at t=100000, process 5 end at t=400006: Cycle forbidden.
 *)
{
 3:r3=x0; x4=y0; 4:r4=y0;
}
 P0            | P1            | P2            | P3                 | P4                 ;
 r[once] r1 x0 | r[once] r1 x1 | r[once] r1 x2 | f[rcu_read_lock]   | f[rcu_read_lock]   ;
 f[sync]       | f[sync]       | f[sync]       | r[once] r1 x3      | r[deref] r1 x4     ;
 w[once] x1 1  | w[once] x2 1  | w[once] x3 1  | w[assign] x4 r3    | w[once] r1 1       ;
               |               |               | f[rcu_read_unlock] | f[rcu_read_unlock] ;
Observed
    4:r1=x0; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=1;
and 4:r1=x0; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=1;
and 4:r1=x0; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=1;
and 4:r1=y0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 4:r1=x0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 4:r1=y0; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=0;
and 4:r1=x0; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=0;
and 4:r1=y0; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=0;
and 4:r1=x0; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=0;
and 4:r1=y0; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=0;
and 4:r1=x0; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=0;