Test auto/RW-G+RW-B+RW-G+RW-G+RW-r+RW-a

LISA auto/RW-G+RW-B+RW-G+RW-G+RW-r+RW-a
(*
 * Result: Never
 * 
 * Process 0 starts (t=100000).
 * 
 * P0 advances one grace period (t=200000).
 * 
 * P1 advances slightly (t=200002).
 * 
 * P2 advances one grace period (t=300003).
 * 
 * P3 advances one grace period (t=400004).
 * 
 * P4 advances slightly (t=400006).
 * 
 * P5 advances slightly (t=400008).
 * 
 * Process 0 start at t=100000, process 6 end at t=400008: Cycle forbidden.
 *)
{
}
 P0            | P1            | P2            | P3            | P4              | P5               ;
 r[once] r1 x0 | r[once] r1 x1 | r[once] r1 x2 | r[once] r1 x3 | r[once] r1 x4   | r[acquire] r1 x5 ;
 f[sync]       | f[mb]         | f[sync]       | f[sync]       | w[release] x5 1 | w[once] x0 1     ;
 w[once] x1 1  | w[once] x2 1  | w[once] x3 1  | w[once] x4 1  |                 |                  ;
Observed
    5:r1=0; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=0; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=0; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=0; 4:r1=0; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=0; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=1;
and 5:r1=1; 4:r1=0; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=1;
and 5:r1=0; 4:r1=0; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=0; 0:r1=1;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=0; 0:r1=1;
and 5:r1=1; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=0; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=0; 3:r1=0; 2:r1=1; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=0; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=0; 3:r1=1; 2:r1=0; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=0;
and 5:r1=0; 4:r1=0; 3:r1=0; 2:r1=0; 1:r1=1; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=0;
and 5:r1=0; 4:r1=0; 3:r1=1; 2:r1=1; 1:r1=0; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=1; 1:r1=0; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=0;
and 5:r1=1; 4:r1=0; 3:r1=1; 2:r1=0; 1:r1=0; 0:r1=0;
and 5:r1=1; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=0; 0:r1=0;
and 5:r1=0; 4:r1=1; 3:r1=0; 2:r1=0; 1:r1=0; 0:r1=0;