Test auto/RR-R+RR-R+RR-R+RR-R+RR-R

LISA auto/RR-R+RR-R+RR-R+RR-R+RR-R
(*
 * Result: Sometimes
 * 
 * Process 0 starts (t=594996).
 * 
 * P0 goes back a bit less than one grace period (t=495996).
 * 
 * P1 goes back a bit less than one grace period (t=396997).
 * 
 * P2 goes back a bit less than one grace period (t=297998).
 * 
 * P3 goes back a bit less than one grace period (t=198999).
 * 
 * P4 goes back a bit less than one grace period (t=100000).
 * 
 * Process 0 start at t=594996, process 5 end at t=100000: Cycle allowed.
 *)
{
}
 P0                 | P1                 | P2                 | P3                 | P4                 | P5           ;
 f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   | f[rcu_read_lock]   | w[once] x0 1 ;
 r[once] r1 x0      | r[once] r1 x1      | r[once] r1 x2      | r[once] r1 x3      | r[once] r1 x4      | w[once] x1 1 ;
 r[once] r2 x1      | r[once] r2 x2      | r[once] r2 x3      | r[once] r2 x4      | r[once] r2 x0      | w[once] x2 1 ;
 f[rcu_read_unlock] | f[rcu_read_unlock] | f[rcu_read_unlock] | f[rcu_read_unlock] | f[rcu_read_unlock] | w[once] x3 1 ;
                    |                    |                    |                    |                    | w[once] x4 1 ;
Observed
    4:r2=0; 4:r1=1; 3:r2=0; 3:r1=1; 2:r2=0; 2:r1=1; 1:r2=0; 1:r1=1; 0:r2=0; 0:r1=1;