Test auto/RR-GR2+RR-R+RR-R

LISA auto/RR-GR2+RR-R+RR-R
(*
 * Result: Sometimes
 * 
 * Process 0 starts (t=197998).
 * 
 * P0 advances one grace period (t=297998).
 * 
 * P1 goes back a bit less than one grace period (t=198999).
 * 
 * P2 goes back a bit less than one grace period (t=100000).
 * 
 * Process 0 start at t=197998, process 3 end at t=100000: Cycle allowed.
 *)
{
}
 P0                 | P1                 | P2                 | P3           ;
 r[once] r1 x0      | f[rcu_read_lock]   | f[rcu_read_lock]   | w[once] x0 1 ;
 f[sync]            | r[once] r1 x1      | r[once] r1 x2      | w[once] x1 1 ;
 f[rcu_read_lock]   | r[once] r2 x2      | r[once] r2 x0      | w[once] x2 1 ;
 r[once] r2 x1      | f[rcu_read_unlock] | f[rcu_read_unlock] |              ;
 f[rcu_read_unlock] |                    |                    |              ;
Observed
    2:r2=1; 2:r1=1; 1:r2=1; 1:r1=1; 0:r2=0; 0:r1=1;
and 2:r2=0; 2:r1=1; 1:r2=1; 1:r1=1; 0:r2=0; 0:r1=1;
and 2:r2=1; 2:r1=0; 1:r2=1; 1:r1=1; 0:r2=0; 0:r1=1;
and 2:r2=0; 2:r1=0; 1:r2=1; 1:r1=1; 0:r2=0; 0:r1=1;
and 2:r2=1; 2:r1=1; 1:r2=0; 1:r1=1; 0:r2=0; 0:r1=1;
and 2:r2=0; 2:r1=1; 1:r2=0; 1:r1=1; 0:r2=0; 0:r1=1;
and 2:r2=1; 2:r1=0; 1:r2=0; 1:r1=1; 0:r2=0; 0:r1=1;
and 2:r2=0; 2:r1=0; 1:r2=0; 1:r1=1; 0:r2=0; 0:r1=1;
and 2:r2=1; 2:r1=1; 1:r2=1; 1:r1=0; 0:r2=0; 0:r1=1;
and 2:r2=0; 2:r1=1; 1:r2=1; 1:r1=0; 0:r2=0; 0:r1=1;
and 2:r2=1; 2:r1=0; 1:r2=1; 1:r1=0; 0:r2=0; 0:r1=1;
and 2:r2=0; 2:r1=0; 1:r2=1; 1:r1=0; 0:r2=0; 0:r1=1;
and 2:r2=1; 2:r1=1; 1:r2=0; 1:r1=0; 0:r2=0; 0:r1=1;
and 2:r2=0; 2:r1=1; 1:r2=0; 1:r1=0; 0:r2=0; 0:r1=1;
and 2:r2=1; 2:r1=0; 1:r2=0; 1:r1=0; 0:r2=0; 0:r1=1;