LISA LISA2Rec1G (* * Result: Never * * One RCU grace period with a pair of RCU read-side critical sections, * but with P0's memory barrier and RCU read-side critical section * having effect. Cycle forbidden. *) { x0 = 0; x1 = 0; x2 = 0; x3 = 0; } P0 | P1 | P2 ; f[rcu_read_lock] | r[once] r1 x1 | f[rcu_read_lock] ; r[once] r2 x0 | f[sync] | r[once] r2 x3 ; f[mb] | w[once] x3 1 | w[once] x0 1 ; w[once] x1 1 | r[once] r3 x2 | f[rcu_read_unlock] ; w[once] x2 1 | | ; f[rcu_read_unlock] | | ; Observed 2:r2=1; 1:r3=1; 1:r1=0; 0:r2=1;