Test Z6.2+fencemboncerelease+poacquireonce+poacquireonce

C Z6.2+fencemboncerelease+poacquireonce+poacquireonce
Hash=6b68c10e9a552e19438dfce808b688a3
Cycle=PodRWAcquireOnce RfeOnceAcquire PodRWAcquireOnce WseOnceOnce FenceMbdWWOnceRelease RfeReleaseAcquire
Relax=RfeOnceAcquire RfeReleaseAcquire
Safe=FenceMbdWW PodRWAcquireOnce WseOnceOnce
Generator=diy7 (version 7.46+3)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Ws
Orig=FenceMbdWWOnceRelease RfeReleaseAcquire PodRWAcquireOnce RfeOnceAcquire PodRWAcquireOnce WseOnceOnce

{}


P0(int* x,int* y) {
  WRITE_ONCE(*x,2);
  smp_mb();
  smp_store_release(y,1);
}

P1(int* y,int* z) {
  int r0 = smp_load_acquire(y);
  WRITE_ONCE(*z,1);
}

P2(int* x,int* z) {
  int r0 = smp_load_acquire(z);
  WRITE_ONCE(*x,1);
}

Observed
    x=2; 2:r0=1; 1:r0=1;

C11 equivalent:

C Z6.2+fencemboncerelease+poacquireonce+poacquireonce
Hash=6b68c10e9a552e19438dfce808b688a3
Cycle=PodRWAcquireOnce RfeOnceAcquire PodRWAcquireOnce WseOnceOnce FenceMbdWWOnceRelease RfeReleaseAcquire
Relax=RfeOnceAcquire RfeReleaseAcquire
Safe=FenceMbdWW PodRWAcquireOnce WseOnceOnce
Generator=diy7 (version 7.46+3)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Rf Rf Ws
Orig=FenceMbdWWOnceRelease RfeReleaseAcquire PodRWAcquireOnce RfeOnceAcquire PodRWAcquireOnce WseOnceOnce

{}


P0(atomic_int* x,atomic_int* y) {
  atomic_store_explicit(x,2,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  atomic_store_explicit(y,1,memory_order_release);
}

P1(atomic_int* y,atomic_int* z) {
  int r0 = atomic_load_explicit(y,memory_order_acquire);
  atomic_store_explicit(z,1,memory_order_relaxed);
}

P2(atomic_int* x,atomic_int* z) {
  int r0 = atomic_load_explicit(z,memory_order_acquire);
  atomic_store_explicit(x,1,memory_order_relaxed);
}

exists (x=2 /\ 1:r0=1 /\ 2:r0=1)