Test Z6.0+poreleaserelease+fencembacquireonce+fencembreleaseonce

C Z6.0+poreleaserelease+fencembacquireonce+fencembreleaseonce
Hash=8d7fd4890261bc95f08dd987cad810ce
Cycle=FenceMbdRWAcquireOnce WseOnceRelease FenceMbdWRReleaseOnce FreOnceRelease PodWWReleaseRelease RfeReleaseAcquire
Relax=FreOnceRelease WseOnceRelease RfeReleaseAcquire
Safe=FenceMbdWR FenceMbdRW PodWWReleaseRelease
Generator=diy7 (version 7.46+3)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Ws Fr
Orig=PodWWReleaseRelease RfeReleaseAcquire FenceMbdRWAcquireOnce WseOnceRelease FenceMbdWRReleaseOnce FreOnceRelease

{}


P0(int* x,int* y) {
  smp_store_release(x,1);
  smp_store_release(y,1);
}

P1(int* y,int* z) {
  int r0 = smp_load_acquire(y);
  smp_mb();
  WRITE_ONCE(*z,1);
}

P2(int* x,int* z) {
  smp_store_release(z,2);
  smp_mb();
  int r0 = READ_ONCE(*x);
}

Observed
    z=2; 2:r0=0; 1:r0=1;

C11 equivalent:

C Z6.0+poreleaserelease+fencembacquireonce+fencembreleaseonce
Hash=8d7fd4890261bc95f08dd987cad810ce
Cycle=FenceMbdRWAcquireOnce WseOnceRelease FenceMbdWRReleaseOnce FreOnceRelease PodWWReleaseRelease RfeReleaseAcquire
Relax=FreOnceRelease WseOnceRelease RfeReleaseAcquire
Safe=FenceMbdWR FenceMbdRW PodWWReleaseRelease
Generator=diy7 (version 7.46+3)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Ws Fr
Orig=PodWWReleaseRelease RfeReleaseAcquire FenceMbdRWAcquireOnce WseOnceRelease FenceMbdWRReleaseOnce FreOnceRelease

{}


P0(atomic_int* x,atomic_int* y) {
  atomic_store_explicit(x,1,memory_order_release);
  atomic_store_explicit(y,1,memory_order_release);
}

P1(atomic_int* y,atomic_int* z) {
  int r0 = atomic_load_explicit(y,memory_order_acquire);
  atomic_thread_fence(memory_order_seq_cst);
  atomic_store_explicit(z,1,memory_order_relaxed);
}

P2(atomic_int* x,atomic_int* z) {
  atomic_store_explicit(z,2,memory_order_release);
  atomic_thread_fence(memory_order_seq_cst);
  int r0 = atomic_load_explicit(x,memory_order_relaxed);
}

exists (z=2 /\ 1:r0=1 /\ 2:r0=0)