Test Z6.0+pooncerelease+fencembonceonce+fencembonceacquire

C Z6.0+pooncerelease+fencembonceonce+fencembonceacquire
Hash=de04e1d2078e7c5a2ea1b4b1d5a6159b
Cycle=FreAcquireOnce PodWWOnceRelease RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce FenceMbdWROnceAcquire
Relax=FreAcquireOnce RfeReleaseOnce
Safe=FenceMbdWR FenceMbdRW WseOnceOnce PodWWOnceRelease
Generator=diy7 (version 7.46+3)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Ws Fr
Orig=PodWWOnceRelease RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce FenceMbdWROnceAcquire FreAcquireOnce

{}


P0(int* x,int* y) {
  WRITE_ONCE(*x,1);
  smp_store_release(y,1);
}

P1(int* y,int* z) {
  int r0 = READ_ONCE(*y);
  smp_mb();
  WRITE_ONCE(*z,1);
}

P2(int* x,int* z) {
  WRITE_ONCE(*z,2);
  smp_mb();
  int r0 = smp_load_acquire(x);
}

Observed
    z=2; 2:r0=0; 1:r0=1;

C11 equivalent:

C Z6.0+pooncerelease+fencembonceonce+fencembonceacquire
Hash=de04e1d2078e7c5a2ea1b4b1d5a6159b
Cycle=FreAcquireOnce PodWWOnceRelease RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce FenceMbdWROnceAcquire
Relax=FreAcquireOnce RfeReleaseOnce
Safe=FenceMbdWR FenceMbdRW WseOnceOnce PodWWOnceRelease
Generator=diy7 (version 7.46+3)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T
Com=Rf Ws Fr
Orig=PodWWOnceRelease RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce FenceMbdWROnceAcquire FreAcquireOnce

{}


P0(atomic_int* x,atomic_int* y) {
  atomic_store_explicit(x,1,memory_order_relaxed);
  atomic_store_explicit(y,1,memory_order_release);
}

P1(atomic_int* y,atomic_int* z) {
  int r0 = atomic_load_explicit(y,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  atomic_store_explicit(z,1,memory_order_relaxed);
}

P2(atomic_int* x,atomic_int* z) {
  atomic_store_explicit(z,2,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  int r0 = atomic_load_explicit(x,memory_order_acquire);
}

exists (z=2 /\ 1:r0=1 /\ 2:r0=0)