C WRW+WR+fencembonceonce+fencembonceacquire+Release Hash=c6f568c0713e3ea832d6a40eb21931e9 Cycle=FreAcquireRelease RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce FenceMbdWROnceAcquire Relax=FreAcquireRelease RfeReleaseOnce Safe=FenceMbdWR FenceMbdRW WseOnceOnce Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=W,2:y=F,2:x=T Com=Rf Ws Fr Orig=RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce FenceMbdWROnceAcquire FreAcquireRelease {} P0(int* x) { smp_store_release(x,1); } P1(int* x,int* y) { int r0 = READ_ONCE(*x); smp_mb(); WRITE_ONCE(*y,1); } P2(int* x,int* y) { WRITE_ONCE(*y,2); smp_mb(); int r0 = smp_load_acquire(x); } Observed y=2; 2:r0=0; 1:r0=1;
C11 equivalent:
C WRW+WR+fencembonceonce+fencembonceacquire+Release Hash=c6f568c0713e3ea832d6a40eb21931e9 Cycle=FreAcquireRelease RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce FenceMbdWROnceAcquire Relax=FreAcquireRelease RfeReleaseOnce Safe=FenceMbdWR FenceMbdRW WseOnceOnce Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=W,2:y=F,2:x=T Com=Rf Ws Fr Orig=RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce FenceMbdWROnceAcquire FreAcquireRelease {} P0(atomic_int* x) { atomic_store_explicit(x,1,memory_order_release); } P1(atomic_int* x,atomic_int* y) { int r0 = atomic_load_explicit(x,memory_order_relaxed); atomic_thread_fence(memory_order_seq_cst); atomic_store_explicit(y,1,memory_order_relaxed); } P2(atomic_int* x,atomic_int* y) { atomic_store_explicit(y,2,memory_order_relaxed); atomic_thread_fence(memory_order_seq_cst); int r0 = atomic_load_explicit(x,memory_order_acquire); } exists (y=2 /\ 1:r0=1 /\ 2:r0=0)