C WRR+2W+fencembonceonce+fencembreleaseonce+Release Hash=5d2dd1e258fb838f3c3919bc7a3fe83a Cycle=FenceMbdRROnceOnce FreOnceRelease FenceMbdWWReleaseOnce WseOnceRelease RfeReleaseOnce Relax=FreOnceRelease WseOnceRelease RfeReleaseOnce Safe=FenceMbdWW FenceMbdRR Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=T,2:y=F,2:x=W Com=Rf Fr Ws Orig=RfeReleaseOnce FenceMbdRROnceOnce FreOnceRelease FenceMbdWWReleaseOnce WseOnceRelease {} P0(int* x) { smp_store_release(x,2); } P1(int* x,int* y) { int r0 = READ_ONCE(*x); smp_mb(); int r1 = READ_ONCE(*y); } P2(int* x,int* y) { smp_store_release(y,1); smp_mb(); WRITE_ONCE(*x,1); } Observed x=2; 1:r1=0; 1:r0=2;
C11 equivalent:
C WRR+2W+fencembonceonce+fencembreleaseonce+Release Hash=5d2dd1e258fb838f3c3919bc7a3fe83a Cycle=FenceMbdRROnceOnce FreOnceRelease FenceMbdWWReleaseOnce WseOnceRelease RfeReleaseOnce Relax=FreOnceRelease WseOnceRelease RfeReleaseOnce Safe=FenceMbdWW FenceMbdRR Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=T,2:y=F,2:x=W Com=Rf Fr Ws Orig=RfeReleaseOnce FenceMbdRROnceOnce FreOnceRelease FenceMbdWWReleaseOnce WseOnceRelease {} P0(atomic_int* x) { atomic_store_explicit(x,2,memory_order_release); } P1(atomic_int* x,atomic_int* y) { int r0 = atomic_load_explicit(x,memory_order_relaxed); atomic_thread_fence(memory_order_seq_cst); int r1 = atomic_load_explicit(y,memory_order_relaxed); } P2(atomic_int* x,atomic_int* y) { atomic_store_explicit(y,1,memory_order_release); atomic_thread_fence(memory_order_seq_cst); atomic_store_explicit(x,1,memory_order_relaxed); } exists (x=2 /\ 1:r0=2 /\ 1:r1=0)