Test WRR+2W+fencembonceacquire+fencemboncerelease+Release

C WRR+2W+fencembonceacquire+fencemboncerelease+Release
Hash=d0c67afe2c3c8735bd7ed5eb5808b0b1
Cycle=FreAcquireOnce FenceMbdWWOnceRelease WseReleaseRelease RfeReleaseOnce FenceMbdRROnceAcquire
Relax=FreAcquireOnce RfeReleaseOnce WseReleaseRelease
Safe=FenceMbdWW FenceMbdRR
Generator=diy7 (version 7.46+3)
Prefetch=1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=RfeReleaseOnce FenceMbdRROnceAcquire FreAcquireOnce FenceMbdWWOnceRelease WseReleaseRelease

{}


P0(int* x) {
  smp_store_release(x,2);
}

P1(int* x,int* y) {
  int r0 = READ_ONCE(*x);
  smp_mb();
  int r1 = smp_load_acquire(y);
}

P2(int* x,int* y) {
  WRITE_ONCE(*y,1);
  smp_mb();
  smp_store_release(x,1);
}

Observed
    x=2; 1:r1=0; 1:r0=2;

C11 equivalent:

C WRR+2W+fencembonceacquire+fencemboncerelease+Release
Hash=d0c67afe2c3c8735bd7ed5eb5808b0b1
Cycle=FreAcquireOnce FenceMbdWWOnceRelease WseReleaseRelease RfeReleaseOnce FenceMbdRROnceAcquire
Relax=FreAcquireOnce RfeReleaseOnce WseReleaseRelease
Safe=FenceMbdWW FenceMbdRR
Generator=diy7 (version 7.46+3)
Prefetch=1:x=F,1:y=T,2:y=F,2:x=W
Com=Rf Fr Ws
Orig=RfeReleaseOnce FenceMbdRROnceAcquire FreAcquireOnce FenceMbdWWOnceRelease WseReleaseRelease

{}


P0(atomic_int* x) {
  atomic_store_explicit(x,2,memory_order_release);
}

P1(atomic_int* x,atomic_int* y) {
  int r0 = atomic_load_explicit(x,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  int r1 = atomic_load_explicit(y,memory_order_acquire);
}

P2(atomic_int* x,atomic_int* y) {
  atomic_store_explicit(y,1,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  atomic_store_explicit(x,1,memory_order_release);
}

exists (x=2 /\ 1:r0=2 /\ 1:r1=0)