C S+fencembonceonce+pooncerelease Hash=a0d472606296e877ea0639999b0ba2b3 Cycle=RfeOnceOnce PodRWOnceRelease WseReleaseOnce FenceMbdWWOnceOnce Relax=WseReleaseOnce Safe=FenceMbdWW RfeOnceOnce PodRWOnceRelease Generator=diy7 (version 7.46+3) Prefetch=0:x=F,0:y=W,1:y=F,1:x=W Com=Rf Ws Orig=FenceMbdWWOnceOnce RfeOnceOnce PodRWOnceRelease WseReleaseOnce {} P0(int* x,int* y) { WRITE_ONCE(*x,2); smp_mb(); WRITE_ONCE(*y,1); } P1(int* x,int* y) { int r0 = READ_ONCE(*y); smp_store_release(x,1); } Observed x=2; 1:r0=1;
C11 equivalent:
C S+fencembonceonce+pooncerelease Hash=a0d472606296e877ea0639999b0ba2b3 Cycle=RfeOnceOnce PodRWOnceRelease WseReleaseOnce FenceMbdWWOnceOnce Relax=WseReleaseOnce Safe=FenceMbdWW RfeOnceOnce PodRWOnceRelease Generator=diy7 (version 7.46+3) Prefetch=0:x=F,0:y=W,1:y=F,1:x=W Com=Rf Ws Orig=FenceMbdWWOnceOnce RfeOnceOnce PodRWOnceRelease WseReleaseOnce {} P0(atomic_int* x,atomic_int* y) { atomic_store_explicit(x,2,memory_order_relaxed); atomic_thread_fence(memory_order_seq_cst); atomic_store_explicit(y,1,memory_order_relaxed); } P1(atomic_int* x,atomic_int* y) { int r0 = atomic_load_explicit(y,memory_order_relaxed); atomic_store_explicit(x,1,memory_order_release); } exists (x=2 /\ 1:r0=1)