Test RWC+fencembonceacquires+Release

C RWC+fencembonceacquires+Release
Hash=614ad22ad2d16c4b4b93ac8ace3b4c05
Cycle=FreAcquireOnce FenceMbdWROnceAcquire FreAcquireRelease RfeReleaseOnce FenceMbdRROnceAcquire
Relax=FreAcquireOnce FreAcquireRelease RfeReleaseOnce
Safe=FenceMbdWR FenceMbdRR
Generator=diy7 (version 7.46+3)
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=RfeReleaseOnce FenceMbdRROnceAcquire FreAcquireOnce FenceMbdWROnceAcquire FreAcquireRelease

{}


P0(int* x) {
  smp_store_release(x,1);
}

P1(int* x,int* y) {
  int r0 = READ_ONCE(*x);
  smp_mb();
  int r1 = smp_load_acquire(y);
}

P2(int* x,int* y) {
  WRITE_ONCE(*y,1);
  smp_mb();
  int r0 = smp_load_acquire(x);
}

Observed
    2:r0=0; 1:r1=0; 1:r0=1;

C11 equivalent:

C RWC+fencembonceacquires+Release
Hash=614ad22ad2d16c4b4b93ac8ace3b4c05
Cycle=FreAcquireOnce FenceMbdWROnceAcquire FreAcquireRelease RfeReleaseOnce FenceMbdRROnceAcquire
Relax=FreAcquireOnce FreAcquireRelease RfeReleaseOnce
Safe=FenceMbdWR FenceMbdRR
Generator=diy7 (version 7.46+3)
Prefetch=1:x=F,1:y=T,2:y=F,2:x=T
Com=Rf Fr Fr
Orig=RfeReleaseOnce FenceMbdRROnceAcquire FreAcquireOnce FenceMbdWROnceAcquire FreAcquireRelease

{}


P0(atomic_int* x) {
  atomic_store_explicit(x,1,memory_order_release);
}

P1(atomic_int* x,atomic_int* y) {
  int r0 = atomic_load_explicit(x,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  int r1 = atomic_load_explicit(y,memory_order_acquire);
}

P2(atomic_int* x,atomic_int* y) {
  atomic_store_explicit(y,1,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  int r0 = atomic_load_explicit(x,memory_order_acquire);
}

exists (1:r0=1 /\ 1:r1=0 /\ 2:r0=0)