C RWC+fencembacquireonce+fencembonceonce+Once Hash=c2001a7e845bcfbfe8e2518c8f15cbbf Cycle=FenceMbdRRAcquireOnce FreOnceOnce FenceMbdWROnceOnce FreOnceOnce RfeOnceAcquire Relax=RfeOnceAcquire Safe=FenceMbdWR FenceMbdRR FreOnceOnce Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=T,2:y=F,2:x=T Com=Rf Fr Fr Orig=RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceOnce FenceMbdWROnceOnce FreOnceOnce {} P0(int* x) { WRITE_ONCE(*x,1); } P1(int* x,int* y) { int r0 = smp_load_acquire(x); smp_mb(); int r1 = READ_ONCE(*y); } P2(int* x,int* y) { WRITE_ONCE(*y,1); smp_mb(); int r0 = READ_ONCE(*x); } Observed 2:r0=0; 1:r1=0; 1:r0=1;
C11 equivalent:
C RWC+fencembacquireonce+fencembonceonce+Once Hash=c2001a7e845bcfbfe8e2518c8f15cbbf Cycle=FenceMbdRRAcquireOnce FreOnceOnce FenceMbdWROnceOnce FreOnceOnce RfeOnceAcquire Relax=RfeOnceAcquire Safe=FenceMbdWR FenceMbdRR FreOnceOnce Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=T,2:y=F,2:x=T Com=Rf Fr Fr Orig=RfeOnceAcquire FenceMbdRRAcquireOnce FreOnceOnce FenceMbdWROnceOnce FreOnceOnce {} P0(atomic_int* x) { atomic_store_explicit(x,1,memory_order_relaxed); } P1(atomic_int* x,atomic_int* y) { int r0 = atomic_load_explicit(x,memory_order_acquire); atomic_thread_fence(memory_order_seq_cst); int r1 = atomic_load_explicit(y,memory_order_relaxed); } P2(atomic_int* x,atomic_int* y) { atomic_store_explicit(y,1,memory_order_relaxed); atomic_thread_fence(memory_order_seq_cst); int r0 = atomic_load_explicit(x,memory_order_relaxed); } exists (1:r0=1 /\ 1:r1=0 /\ 2:r0=0)