C ISA2+fencemboncerelease+pooncerelease+poacquireacquire Hash=c097e2e3d5929456ecd647a372805da7 Cycle=PodRRAcquireAcquire FreAcquireOnce FenceMbdWWOnceRelease RfeReleaseOnce PodRWOnceRelease RfeReleaseAcquire Relax=FreAcquireOnce RfeReleaseAcquire RfeReleaseOnce Safe=FenceMbdWW PodRRAcquireAcquire PodRWOnceRelease Generator=diy7 (version 7.46+3) Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T Com=Rf Rf Fr Orig=FenceMbdWWOnceRelease RfeReleaseOnce PodRWOnceRelease RfeReleaseAcquire PodRRAcquireAcquire FreAcquireOnce {} P0(int* x,int* y) { WRITE_ONCE(*x,1); smp_mb(); smp_store_release(y,1); } P1(int* y,int* z) { int r0 = READ_ONCE(*y); smp_store_release(z,1); } P2(int* x,int* z) { int r0 = smp_load_acquire(z); int r1 = smp_load_acquire(x); } Observed 2:r1=0; 2:r0=1; 1:r0=1;
C11 equivalent:
C ISA2+fencemboncerelease+pooncerelease+poacquireacquire Hash=c097e2e3d5929456ecd647a372805da7 Cycle=PodRRAcquireAcquire FreAcquireOnce FenceMbdWWOnceRelease RfeReleaseOnce PodRWOnceRelease RfeReleaseAcquire Relax=FreAcquireOnce RfeReleaseAcquire RfeReleaseOnce Safe=FenceMbdWW PodRRAcquireAcquire PodRWOnceRelease Generator=diy7 (version 7.46+3) Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=T Com=Rf Rf Fr Orig=FenceMbdWWOnceRelease RfeReleaseOnce PodRWOnceRelease RfeReleaseAcquire PodRRAcquireAcquire FreAcquireOnce {} P0(atomic_int* x,atomic_int* y) { atomic_store_explicit(x,1,memory_order_relaxed); atomic_thread_fence(memory_order_seq_cst); atomic_store_explicit(y,1,memory_order_release); } P1(atomic_int* y,atomic_int* z) { int r0 = atomic_load_explicit(y,memory_order_relaxed); atomic_store_explicit(z,1,memory_order_release); } P2(atomic_int* x,atomic_int* z) { int r0 = atomic_load_explicit(z,memory_order_acquire); int r1 = atomic_load_explicit(x,memory_order_acquire); } exists (1:r0=1 /\ 2:r0=1 /\ 2:r1=0)