C IRWIW+pooncerelease+fencembonceonce+OnceRelease Hash=a1dc2fb176744df4d41b122bb6e3d11f Cycle=RfeOnceOnce PodRWOnceRelease WseReleaseRelease RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce Relax=RfeReleaseOnce WseReleaseRelease Safe=FenceMbdRW RfeOnceOnce WseOnceOnce PodRWOnceRelease Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=W,3:y=F,3:x=W Com=Rf Ws Rf Ws Orig=RfeOnceOnce PodRWOnceRelease WseReleaseRelease RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce {} P0(int* x) { WRITE_ONCE(*x,2); } P1(int* x,int* y) { int r0 = READ_ONCE(*x); smp_store_release(y,1); } P2(int* y) { smp_store_release(y,2); } P3(int* x,int* y) { int r0 = READ_ONCE(*y); smp_mb(); WRITE_ONCE(*x,1); } Observed y=2; x=2; 3:r0=2; 1:r0=1; and y=2; x=1; 3:r0=2; 1:r0=1;
C11 equivalent:
C IRWIW+pooncerelease+fencembonceonce+OnceRelease Hash=a1dc2fb176744df4d41b122bb6e3d11f Cycle=RfeOnceOnce PodRWOnceRelease WseReleaseRelease RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce Relax=RfeReleaseOnce WseReleaseRelease Safe=FenceMbdRW RfeOnceOnce WseOnceOnce PodRWOnceRelease Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=W,3:y=F,3:x=W Com=Rf Ws Rf Ws Orig=RfeOnceOnce PodRWOnceRelease WseReleaseRelease RfeReleaseOnce FenceMbdRWOnceOnce WseOnceOnce {} P0(atomic_int* x) { atomic_store_explicit(x,2,memory_order_relaxed); } P1(atomic_int* x,atomic_int* y) { int r0 = atomic_load_explicit(x,memory_order_relaxed); atomic_store_explicit(y,1,memory_order_release); } P2(atomic_int* y) { atomic_store_explicit(y,2,memory_order_release); } P3(atomic_int* x,atomic_int* y) { int r0 = atomic_load_explicit(y,memory_order_relaxed); atomic_thread_fence(memory_order_seq_cst); atomic_store_explicit(x,1,memory_order_relaxed); } exists (x=2 /\ y=2 /\ 1:r0=2 /\ 3:r0=2)