C IRWIW+fencemboncerelease+pooncerelease+ReleaseRelease Hash=ec71c1f68f38f0a2047e908482145eee Cycle=PodRWOnceRelease WseReleaseRelease RfeReleaseOnce FenceMbdRWOnceRelease WseReleaseRelease RfeReleaseOnce Relax=RfeReleaseOnce WseReleaseRelease Safe=FenceMbdRW PodRWOnceRelease Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=W,3:y=F,3:x=W Com=Rf Ws Rf Ws Orig=RfeReleaseOnce FenceMbdRWOnceRelease WseReleaseRelease RfeReleaseOnce PodRWOnceRelease WseReleaseRelease {} P0(int* x) { smp_store_release(x,2); } P1(int* x,int* y) { int r0 = READ_ONCE(*x); smp_mb(); smp_store_release(y,1); } P2(int* y) { smp_store_release(y,2); } P3(int* x,int* y) { int r0 = READ_ONCE(*y); smp_store_release(x,1); } Observed y=2; x=2; 3:r0=1; 1:r0=2; and y=1; x=2; 3:r0=1; 1:r0=2;
C11 equivalent:
C IRWIW+fencemboncerelease+pooncerelease+ReleaseRelease Hash=ec71c1f68f38f0a2047e908482145eee Cycle=PodRWOnceRelease WseReleaseRelease RfeReleaseOnce FenceMbdRWOnceRelease WseReleaseRelease RfeReleaseOnce Relax=RfeReleaseOnce WseReleaseRelease Safe=FenceMbdRW PodRWOnceRelease Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=W,3:y=F,3:x=W Com=Rf Ws Rf Ws Orig=RfeReleaseOnce FenceMbdRWOnceRelease WseReleaseRelease RfeReleaseOnce PodRWOnceRelease WseReleaseRelease {} P0(atomic_int* x) { atomic_store_explicit(x,2,memory_order_release); } P1(atomic_int* x,atomic_int* y) { int r0 = atomic_load_explicit(x,memory_order_relaxed); atomic_thread_fence(memory_order_seq_cst); atomic_store_explicit(y,1,memory_order_release); } P2(atomic_int* y) { atomic_store_explicit(y,2,memory_order_release); } P3(atomic_int* x,atomic_int* y) { int r0 = atomic_load_explicit(y,memory_order_relaxed); atomic_store_explicit(x,1,memory_order_release); } exists (x=2 /\ y=2 /\ 1:r0=2 /\ 3:r0=2)