Test IRWIW+fencembacquireonce+pooncerelease+OnceOnce

C IRWIW+fencembacquireonce+pooncerelease+OnceOnce
Hash=c5f27d2cf95879481f9610bcf19031e3
Cycle=FenceMbdRWAcquireOnce WseOnceOnce RfeOnceOnce PodRWOnceRelease WseReleaseOnce RfeOnceAcquire
Relax=RfeOnceAcquire WseReleaseOnce
Safe=FenceMbdRW RfeOnceOnce WseOnceOnce PodRWOnceRelease
Generator=diy7 (version 7.46+3)
Prefetch=1:x=F,1:y=W,3:y=F,3:x=W
Com=Rf Ws Rf Ws
Orig=RfeOnceAcquire FenceMbdRWAcquireOnce WseOnceOnce RfeOnceOnce PodRWOnceRelease WseReleaseOnce

{}


P0(int* x) {
  WRITE_ONCE(*x,2);
}

P1(int* x,int* y) {
  int r0 = smp_load_acquire(x);
  smp_mb();
  WRITE_ONCE(*y,1);
}

P2(int* y) {
  WRITE_ONCE(*y,2);
}

P3(int* x,int* y) {
  int r0 = READ_ONCE(*y);
  smp_store_release(x,1);
}

Observed
    y=2; x=2; 3:r0=1; 1:r0=2;
and y=1; x=2; 3:r0=1; 1:r0=2;

C11 equivalent:

C IRWIW+fencembacquireonce+pooncerelease+OnceOnce
Hash=c5f27d2cf95879481f9610bcf19031e3
Cycle=FenceMbdRWAcquireOnce WseOnceOnce RfeOnceOnce PodRWOnceRelease WseReleaseOnce RfeOnceAcquire
Relax=RfeOnceAcquire WseReleaseOnce
Safe=FenceMbdRW RfeOnceOnce WseOnceOnce PodRWOnceRelease
Generator=diy7 (version 7.46+3)
Prefetch=1:x=F,1:y=W,3:y=F,3:x=W
Com=Rf Ws Rf Ws
Orig=RfeOnceAcquire FenceMbdRWAcquireOnce WseOnceOnce RfeOnceOnce PodRWOnceRelease WseReleaseOnce

{}


P0(atomic_int* x) {
  atomic_store_explicit(x,2,memory_order_relaxed);
}

P1(atomic_int* x,atomic_int* y) {
  int r0 = atomic_load_explicit(x,memory_order_acquire);
  atomic_thread_fence(memory_order_seq_cst);
  atomic_store_explicit(y,1,memory_order_relaxed);
}

P2(atomic_int* y) {
  atomic_store_explicit(y,2,memory_order_relaxed);
}

P3(atomic_int* x,atomic_int* y) {
  int r0 = atomic_load_explicit(y,memory_order_relaxed);
  atomic_store_explicit(x,1,memory_order_release);
}

exists (x=2 /\ y=2 /\ 1:r0=2 /\ 3:r0=2)