C IRIW+fencembonceacquires+OnceRelease Hash=ef447018ba7b81aee52c5e43eb4e38d7 Cycle=FreAcquireOnce RfeOnceOnce FenceMbdRROnceAcquire FreAcquireRelease RfeReleaseOnce FenceMbdRROnceAcquire Relax=FreAcquireOnce FreAcquireRelease RfeReleaseOnce Safe=FenceMbdRR RfeOnceOnce Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=T,3:y=F,3:x=T Com=Rf Fr Rf Fr Orig=RfeOnceOnce FenceMbdRROnceAcquire FreAcquireRelease RfeReleaseOnce FenceMbdRROnceAcquire FreAcquireOnce {} P0(int* x) { WRITE_ONCE(*x,1); } P1(int* x,int* y) { int r0 = READ_ONCE(*x); smp_mb(); int r1 = smp_load_acquire(y); } P2(int* y) { smp_store_release(y,1); } P3(int* x,int* y) { int r0 = READ_ONCE(*y); smp_mb(); int r1 = smp_load_acquire(x); } Observed 3:r1=0; 3:r0=1; 1:r1=0; 1:r0=1;
C11 equivalent:
C IRIW+fencembonceacquires+OnceRelease Hash=ef447018ba7b81aee52c5e43eb4e38d7 Cycle=FreAcquireOnce RfeOnceOnce FenceMbdRROnceAcquire FreAcquireRelease RfeReleaseOnce FenceMbdRROnceAcquire Relax=FreAcquireOnce FreAcquireRelease RfeReleaseOnce Safe=FenceMbdRR RfeOnceOnce Generator=diy7 (version 7.46+3) Prefetch=1:x=F,1:y=T,3:y=F,3:x=T Com=Rf Fr Rf Fr Orig=RfeOnceOnce FenceMbdRROnceAcquire FreAcquireRelease RfeReleaseOnce FenceMbdRROnceAcquire FreAcquireOnce {} P0(atomic_int* x) { atomic_store_explicit(x,1,memory_order_relaxed); } P1(atomic_int* x,atomic_int* y) { int r0 = atomic_load_explicit(x,memory_order_relaxed); atomic_thread_fence(memory_order_seq_cst); int r1 = atomic_load_explicit(y,memory_order_acquire); } P2(atomic_int* y) { atomic_store_explicit(y,1,memory_order_release); } P3(atomic_int* x,atomic_int* y) { int r0 = atomic_load_explicit(y,memory_order_relaxed); atomic_thread_fence(memory_order_seq_cst); int r1 = atomic_load_explicit(x,memory_order_acquire); } exists (1:r0=1 /\ 1:r1=0 /\ 3:r0=1 /\ 3:r1=0)