Test Z6.1+fencemb+fencewmb+fencemb

C Z6.1+fencemb+fencewmb+fencemb
Hash=3c396831c67ff5204c937bf46c3ef5a8
Cycle=Rfe FenceMbdRW Wse FenceMbdWW Wse FenceWmbdWW
Relax=
Safe=Rfe Wse FenceMbdWW FenceMbdRW FenceWmbdWW
Generator=diy7 (version 7.46+1)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Ws Rf Ws
Orig=FenceMbdWW Wse FenceWmbdWW Rfe FenceMbdRW Wse

{}


P0(int* x,int* y) {
  WRITE_ONCE(*x,2);
  smp_mb();
  WRITE_ONCE(*y,1);
}

P1(int* y,int* z) {
  WRITE_ONCE(*y,2);
  smp_wmb();
  WRITE_ONCE(*z,1);
}

P2(int* x,int* z) {
  int r0 = READ_ONCE(*z);
  smp_mb();
  WRITE_ONCE(*x,1);
}

Observed
    y=2; x=2; 2:r0=1;

C11 equivalent:

C Z6.1+fencemb+fencewmb+fencemb
Hash=3c396831c67ff5204c937bf46c3ef5a8
Cycle=Rfe FenceMbdRW Wse FenceMbdWW Wse FenceWmbdWW
Relax=
Safe=Rfe Wse FenceMbdWW FenceMbdRW FenceWmbdWW
Generator=diy7 (version 7.46+1)
Prefetch=0:x=F,0:y=W,1:y=F,1:z=W,2:z=F,2:x=W
Com=Ws Rf Ws
Orig=FenceMbdWW Wse FenceWmbdWW Rfe FenceMbdRW Wse

{}


P0(atomic_int* x,atomic_int* y) {
  atomic_store_explicit(x,2,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  atomic_store_explicit(y,1,memory_order_relaxed);
}

P1(atomic_int* y,atomic_int* z) {
  atomic_store_explicit(y,2,memory_order_relaxed);
  atomic_thread_fence(memory_order_acq_rel);
  atomic_store_explicit(z,1,memory_order_relaxed);
}

P2(atomic_int* x,atomic_int* z) {
  int r0 = atomic_load_explicit(z,memory_order_relaxed);
  atomic_thread_fence(memory_order_seq_cst);
  atomic_store_explicit(x,1,memory_order_relaxed);
}

exists (x=2 /\ y=2 /\ 2:r0=1)