Test ISA12

Successful load reserve–store conditional pair, with store by the same thread in-between, Allow.

RISCV ISA12

{
uint64_t x;
0:a0=x;
}

 P0               ;
 li t1,1          ;
 li t2,2          ;
 lr.d t0,0(a0)    ;
 sd t1,0(a0)      ;
 sc.d t3,t2,0(a0) ;

locations [0:t3;]
exists x=2