Test WWC+poxxs+X

AArch64 WWC+poxxs+X
"RfeXX PodRWXX RfeXX PodRWXX WseXX"
Cycle=RfeXX PodRWXX RfeXX PodRWXX WseXX
Relax=
Safe=PodRW RfeXX WseXX
Prefetch=1:x=F,1:y=W,2:y=F,2:x=W
Com=Rf Rf Ws
Orig=RfeXX PodRWXX RfeXX PodRWXX WseXX
{ ok=1;
0:X0=x; 0:X5=ok;
1:X0=x; 1:X3=y; 1:X7=ok;
2:X0=y; 2:X3=x; 2:X7=ok;
}
 P0              | P1              | P2              ;
 MOV W1,#2       | LDXR W1,[X0]    | LDXR W1,[X0]    ;
 LDXR W2,[X0]    | STXR W2,W1,[X0] | STXR W2,W1,[X0] ;
 STXR W3,W1,[X0] | CBNZ W2,Fail1   | CBNZ W2,Fail2   ;
 CBNZ W3,Fail0   | MOV W4,#1       | MOV W4,#1       ;
 B Exit0         | LDXR W5,[X3]    | LDXR W5,[X3]    ;
 Fail0:          | STXR W2,W4,[X3] | STXR W2,W4,[X3] ;
 MOV W4,#0       | CBNZ W2,Fail1   | CBNZ W2,Fail2   ;
 STR W4,[X5]     | B Exit1         | B Exit2         ;
 Exit0:          | Fail1:          | Fail2:          ;
                 | MOV W6,#0       | MOV W6,#0       ;
                 | STR W6,[X7]     | STR W6,[X7]     ;
                 | Exit1:          | Exit2:          ;
Observed
    y=1; x=2; ok=1; 2:X5=0; 2:X1=1; 1:X5=0; 1:X1=2; 0:X2=1;
and y=1; x=2; ok=1; 2:X5=0; 2:X1=1; 1:X5=0; 1:X1=1; 0:X2=1;
and y=1; x=1; ok=0; 2:X5=0; 2:X1=1; 1:X5=0; 1:X1=1; 0:X2=1;
and y=1; x=1; ok=1; 2:X5=2; 2:X1=1; 1:X5=0; 1:X1=1; 0:X2=0;
and y=1; x=1; ok=0; 2:X5=0; 2:X1=1; 1:X5=0; 1:X1=1; 0:X2=0;