Test MP+poxxs

AArch64 MP+poxxs
"PodWWXX RfeXX PodRRXX FreXX"
Cycle=RfeXX PodRRXX FreXX PodWWXX
Relax=
Safe=PodWW PodRR RfeXX FreXX
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=PodWWXX RfeXX PodRRXX FreXX
{ ok=1;
0:X0=x; 0:X4=y; 0:X8=ok;
1:X0=y; 1:X3=x; 1:X6=ok;
}
 P0              | P1              ;
 MOV W1,#1       | LDXR W1,[X0]    ;
 LDXR W2,[X0]    | STXR W2,W1,[X0] ;
 STXR W3,W1,[X0] | CBNZ W2,Fail1   ;
 CBNZ W3,Fail0   | LDXR W4,[X3]    ;
 MOV W5,#1       | STXR W2,W4,[X3] ;
 LDXR W6,[X4]    | CBNZ W2,Fail1   ;
 STXR W3,W5,[X4] | B Exit1         ;
 CBNZ W3,Fail0   | Fail1:          ;
 B Exit0         | MOV W5,#0       ;
 Fail0:          | STR W5,[X6]     ;
 MOV W7,#0       | Exit1:          ;
 STR W7,[X8]     |                 ;
 Exit0:          |                 ;
Observed
    y=1; x=1; ok=1; 1:X4=0; 1:X1=1; 0:X6=0; 0:X2=0;