Test MP+dmb.sy+pos-fri-rfi-addr-ctrlisb

AArch64 MP+dmb.sy+pos-fri-rfi-addr-ctrlisb
"DMB.SYdWW Rfe PosRR Fri Rfi DpAddrdR DpCtrlIsbdR Fre"
Cycle=Rfi DpAddrdR DpCtrlIsbdR Fre DMB.SYdWW Rfe PosRR Fri
Relax=
Safe=Rfi Rfe Fri Fre PosRR DMB.SYdWW DpAddrdR DpCtrlIsbdR
Prefetch=0:x=F,0:y=W,1:y=F,1:x=T
Com=Rf Fr
Orig=DMB.SYdWW Rfe PosRR Fri Rfi DpAddrdR DpCtrlIsbdR Fre
{
0:X1=x; 0:X3=y;
1:X1=y; 1:X7=z; 1:X9=x;
}
 P0          | P1                  ;
 MOV W0,#1   | LDR W0,[X1]         ;
 STR W0,[X1] | LDR W2,[X1]         ;
 DMB SY      | MOV W3,#2           ;
 MOV W2,#1   | STR W3,[X1]         ;
 STR W2,[X3] | LDR W4,[X1]         ;
             | EOR W5,W4,W4        ;
             | LDR W6,[X7,W5,SXTW] ;
             | CBNZ W6,LC00        ;
             | LC00:               ;
             | ISB                 ;
             | LDR W8,[X9]         ;
Observed
    y=2; x=1; 1:X8=0; 1:X4=2; 1:X2=1; 1:X0=0;